DDR3 UDIMM 1333Mhz/1600Mhz

• VDD=VDDQ=1.5V (1.48V to 1.57V)

• VDDSPD=3.0V to 3.6V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM masks write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 supported

• Programmable additive latency 0, CL-1, and CL-2 supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• BL switch on the fly

• Average Refresh Cycle - 7.8 μs at 0℃~ 85℃

• JEDEC standard 78ball FBGA(x8)

• Driver strength select by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported • ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• 8 bit pre-fetch

• This product in compliance with the RoHS directive